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About American Electric Power

American Electric Power is an electric utilities company in the United States, delivering electricity to more than 5 million customers in 11 states.

American Electric Power Headquarter Location

1 Riverside Plaza

Columbus, Ohio, 43215,

United States

614-716-1000

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Expert Collections containing American Electric Power

Expert Collections are analyst-curated lists that highlight the companies you need to know in the most important technology spaces.

Find American Electric Power in 2 Expert Collections, including Fortune 500 Investor list.

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This is a collection of investors named in the 2019 Fortune 500 list of companies. All CB Insights profiles for active investment arms of a Fortune 500 company are included.

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This collection includes companies that are working on software and hardware to improve grids, utilizing new pricing models, and developing microgrids. It also includes utilities and energy companies that act as investors.

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Latest American Electric Power News

Former CEO of American Electric Power Dies at 94

Aug 30, 2021

Former CEO of American Electric Power Dies at 94 Share Explore by topic Topics Support IEEE Spectrum IEEE Spectrum is the flagship publication of the IEEE — the world’s largest professional organization devoted to engineering and applied sciences. Our articles, podcasts, and infographics inform our readers about developments in technology, engineering, and science. A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity. IEEE websites place cookies on your device to give you the best user experience. By using our websites, you agree to the placement of these cookies. To learn more, read our Privacy Policy. Saving articles to read later requires an IEEE Spectrum account The Institute content is only available for members Downloading full PDF issues is exclusive for IEEE Members Access to Spectrum's Digital Edition is exclusive for IEEE Members Following topics is a feature exclusive for IEEE Members Adding your response to an article requires an IEEE Spectrum account Create an account to access more content and features on IEEE Spectrum, including the ability to save articles to read later, download Spectrum Collections, and participate in conversations with readers and editors. For more exclusive content and features, consider Joining IEEE . Join the world’s largest professional organization devoted to engineering and applied sciences and get access to all of Spectrum’s articles, archives, PDF downloads, and other benefits. Learn more → Enjoy more free content and benefits by creating an account Create an account to access more content and features on IEEE Spectrum, including the ability to save articles to read later, download Spectrum Collections, and participate in conversations with readers and editors. For more exclusive content and features, consider Joining IEEE . Life senior member, 94; died 4 July White served in the U.S. Navy during World War II. After the war, he joined American Electric Power in Columbus, Ohio, as an assistant engineer. Except for a short period volunteering for the Defense Electric Power Administration during the Korean War, he spent his entire career at AEP. He worked in managerial positions in New York, Ohio, and Virginia, then became AEP's chief executive in 1976 and served in that role until he retired in 1991. He was appointed by U.S. President George H.W. Bush as a private-sector representative to the presidential economic delegation to Poland. White served on the board of visitors at Virginia Tech and was vice rector and rector there. He also served as a director of the Virginia Tech Foundation . He was a trustee of Randolph-Macon Woman's College , in Lynchburg, Va. He earned a bachelor's degree in electrical engineering from the Virginia Polytechnic Institute, now Virginia Tech, and received a master's degree in industrial management as a Sloan Fellow at MIT . He was awarded an honorary doctorate in business administration by Indiana University in Bloomington. He also was a member of the IEEE–Eta Kappa Nu honor society. Member, 92; died 9 March When Dewitt was a youngster, he was an avid sailor and an amateur radio operator. He joined the U.S. Navy after earning a bachelor's degree in electrical engineering in 1951 from Rensselaer Polytechnic Institute , in Troy, N.Y. The Navy assigned him to work at aircraft manufacturer Convair , in San Diego. He was part of a team there developing missile and rocket systems, including the Atlas missile, which was used in Friendship 7 . After DeWitt was discharged from the Navy he left Convair to work on an early digital voltmeter at Electro Instruments. While there, he suggested the company build more accurate calibration systems. But Electro didn't act on his idea, so he left in 1957 to start his own venture, Holt Instrument Laboratories , in his hometown: Oconto, Wis. Holt provided AC and DC voltage and current calibration instruments to all branches of the U.S. military and the companies that served them—including Boeing , Lockheed Martin , and Northrop Grumman . It also was a leader in measurement instruments. Holt supplied calibration and measurement systems used for NASA 's Apollo, Gemini, and Mercury programs, and the company's devices are still used today. Holt helped develop a simulator that trained the Apollo astronauts how to land on the Moon. The company also developed a way to conserve fuel during landing and takeoff of the Apollo 11 lunar landing module. DeWitt downsized his operations after an economic recession hit the United States in 1975. He closed the business in 2018. Fellow, 88; died 18 April Johnson served in the U.S. Army for two years after he earned a bachelor's degree in engineering at the University of California, Los Angeles . While enlisted, he worked on radio electronics for radar vans at the Army's Aberdeen Proving Ground , in Maryland. Following his honorable discharge, he returned to UCLA to pursue a master's degree. After graduating, he joined Collins Radio—now Collins Aerospace —headquartered in Cedar Rapids, Iowa. During his career, he designed 14 patented electromechanical filters. He was an IEEE member for 60 years and presented several papers at the organization's conferences. He also wrote Mechanical Filters in Electronics , the first book in a series about the design, fabrication, and uses of filters. Life senior member, 93; died 16 May Worth was drafted into the U.S. Army in 1950 after receiving a bachelor's degree in electrical engineering in 1949 from Iowa State University , in Ames. He served for two years and was stationed at Fort Monmouth in New Jersey. He left the Army with the rank of sergeant. He briefly worked at Maytag and left the commercial appliance manufacturer to join Iowa Power and Light. He retired from there in 1992. Worth was an avid supporter of the IEEE History Center . Patton's engineering career spanned more than 35 years. He was an electrical engineer for BAE Systems in Nashua, N.H., for 29 years before starting his own Internet marketing consulting business. He was an avid hiker and climbed all 48 1,219-meter-high mountains in New Hampshire, as well as several others in the U.S. National Park System. He received his bachelor's degree in electrical engineering from Drexel University , in Philadelphia, and his master's degree in engineering from Northeastern University , in Boston. The Conversation (0) Get unlimited IEEE Spectrum access Become an IEEE member and get exclusive access to more stories and resources, including our vast article archive and full PDF downloads Network with other technology professionals Establish a professional profile Discover IEEE events and activities Join and participate in discussions DarkGray For a time, each new processor churned out more waste heat than the last. Had these chips kept on the trajectory they were following in the early 2000s, they would soon have packed about 6,400 watts onto each square centimeter—the power flux on the surface of the sun. Things never got that bad because engineers worked to hold down chip power consumption. Data-center system-on-chip (SoC) designs are consistently second only to supercomputer processors in terms of performance, yet they typically consume only about 200 to 400 watts per square centimeter. The chip encased inside that smartphone in your pocket typically draws around 5 W . Nevertheless, while computer chips won't burn a literal hole in your pocket (though they do get hot enough to fry an egg ), they still require a lot of current to run the applications we use every day. Consider the data-center SoC: On average, it's consuming 200 W to provide its transistors with about 1 to 2 volts, which means the chip is drawing 100 to 200 amperes of current from the voltage regulators that supply it. Your typical refrigerator draws only 6 A. High-end mobile phones can draw a tenth as much power as data-center SoCs, but even so that's still about 10–20 A of current. That's up to three refrigerators, in your pocket! Delivering that current to billions of transistors is quickly becoming one of the major bottlenecks in high-performance SoC design. As transistors continue to be made tinier, the interconnects that supply them with current must be packed ever closer and be made ever finer, which increases resistance and saps power. This can't go on: Without a big change in the way electrons get to and from devices on a chip, it won't matter how much smaller we can make transistors. In today's processors both signals and power reach the silicon [light gray] from above. New technology would separate those functions, saving power and making more room for signal routes [right]. Chris Philpot Fortunately, we have a promising solution: We can use a side of the silicon that's long been ignored. Electrons have to travel a long way to get from the source that is generating them to the transistors that compute with them. In most electronics they travel along the copper traces of a printed circuit board into a package that holds the SoC, through the solder balls that connect the chip to the package , and then via on-chip interconnects to the transistors themselves. It's this last stage that really matters. To see why, it helps to understand how chips are made. An SoC starts as a bare piece of high-quality, crystalline silicon. We first make a layer of transistors at the very top of that silicon. Next we link them together with metal interconnects to form circuits with useful computing functions. These interconnects are formed in layers called a stack, and it can take a 10-to-20-layer stack to deliver power and data to the billions of transistors on today's chips. Those layers closest to the silicon transistors are thin and small in order to connect to the tiny transistors, but they grow in size as you go up in the stack to higher levels. It's these levels with broader interconnects that are better at delivering power because they have less resistance. Today, both power and signals reach transistors from a network of interconnects above the silicon (the "front side"). But increasing resistance as these interconnects are scaled down to ever-finer dimensions is making that scheme untenable. Chris Philpot You can see, then, that the metal that powers circuits—the power delivery network (PDN)—is on top of the transistors. We refer to this as front-side power delivery. You can also see that the power network unavoidably competes for space with the network of wires that delivers signals, because they share the same set of copper resources. In order to get power and signals off of the SoC, we typically connect the uppermost layer of metal—farthest away from the transistors—to solder balls (also called bumps) in the chip package. So for electrons to reach any transistor to do useful work, they have to traverse 10 to 20 layers of increasingly narrow and tortuous metal until they can finally squeeze through to the very last layer of local wires. This way of distributing power is fundamentally lossy. At every stage along the path, some power is lost, and some must be used to control the delivery itself. In today's SoCs, designers typically have a budget that allows loss that leads to a 10 percent reduction in voltage between the package and the transistors. Thus, if we hit a total efficiency of 90 percent or greater in a power-delivery network, our designs are on the right track. Historically, such efficiencies have been achievable with good engineering—some might even say it was easy compared to the challenges we face today. In today's electronics, SoC designers not only have to manage increasing power densities but to do so with interconnects that are losing power at a sharply accelerating rate with each new generation. You can design a back-side power delivery network that's up to seven times as efficient as the traditional front-side network. The increasing lossiness has to do with how we make nanoscale wires. That process and its accompanying materials trace back to about 1997, when IBM began to make interconnects out of copper instead of aluminum, and the industry shifted along with it. Up until then aluminum wires had been fine conductors, but in a few more steps along the Moore's Law curve their resistance would soon be too high and become unreliable. Copper is more conductive at modern IC scales. But even copper's resistance began to be problematic once interconnect widths shrank below 100 nanometers. Today, the smallest manufactured interconnects are about 20 nm , so resistance is now an urgent issue. It helps to picture the electrons in an interconnect as a full set of balls on a billiards table. Now imagine shoving them all from one end of the table toward another. A few would collide and bounce against each other on the way, but most would make the journey in a straight-ish line. Now consider shrinking the table by half—you'd get a lot more collisions and the balls would move more slowly. Next, shrink it again and increase the number of billiard balls tenfold, and you're in something like the situation chipmakers face now. Real electrons don't collide, necessarily, but they get close enough to one another to impose a scattering force that disrupts the flow through the wire. At nanoscale dimensions, this leads to vastly higher resistance in the wires, which induces significant power-delivery loss. Increasing electrical resistance is not a new challenge, but the magnitude of increase that we are seeing now with each subsequent process node is unprecedented. Furthermore, traditional ways of managing this increase are no longer an option, because the manufacturing rules at the nanoscale impose so many constraints. Gone are the days when we could arbitrarily increase the widths of certain wires in order to combat increasing resistance. Now designers have to stick to certain specified wire widths or else the chip may not be manufacturable. So, the industry is faced with the twin problems of higher resistance in interconnects and less room for them on the chip. There is another way: We can exploit the "empty" silicon that lies below the transistors. At Imec, where authors Beyne and Zografos work, we have pioneered a manufacturing concept called " buried power rails ," or BPR. The technique builds power connections below the transistors instead of above them, with the aim of creating fatter, less resistant rails and freeing space for signal-carrying interconnects above the transistor layer. To reduce the resistance in power delivery, transistors will tap power rails buried within the silicon. These are relatively large, low-resistance conductors that multiple logic cells could connect with. Chris Philpot To build BPRs, you first have to dig out deep trenches below the transistors and then fill them with metal. You have to do this before you make the transistors themselves. So the metal choice is important. That metal will need to withstand the processing steps used to make high-quality transistors, which can reach about 1,000 °C. At that temperature, copper is molten, and melted copper could contaminate the whole chip. We've therefore experimented with ruthenium and tungsten, which have higher melting points. Since there is so much unused space below the transistors, you can make the BPR trenches wide and deep, which is perfect for delivering power. Compared to the thin metal layers directly on top of the transistors, BPRs can have 1/20 to 1/30 the resistance . That means that BPRs will effectively allow you to deliver more power to the transistors. Furthermore, by moving the power rails off the top side of the transistors you free up room for the signal-carrying interconnects. These interconnects form fundamental circuit "cells"—the smallest circuit units, such as SRAM memory bit cells or simple logic that we use to compose more complex circuits. By using the space we've freed up, we could shrink those cells by 16 percent or more , and that could ultimately translate to more transistors per chip. Even if feature size stayed the same, we'd still push Moore's Law one step further. Unfortunately, it looks like burying local power rails alone won't be enough. You still have to convey power to those rails down from the top side of the chip, and that will cost efficiency and some loss of voltage. Gone are the days when we could arbitrarily increase the widths of certain wires in order to combat increasing resistance. Researchers at Arm, including authors Cline and Prasad, ran a simulation on one of their CPUs and found that, by themselves, BPRs could allow you to build a 40 percent more efficient power network than an ordinary front-side power delivery network. But they also found that even if you used BPRs with front-side power delivery, the overall voltage delivered to the transistors was not high enough to sustain high-performance operation of a CPU. Luckily, Imec was simultaneously developing a complementary solution to further improve power delivery: Move the entire power-delivery network from the front side of the chip to the back side. This solution is called "back-side power delivery," or more generally "back-side metallization." It involves thinning down the silicon that is underneath the transistors to 500 nm or less, at which point you can create nanometer-size "through-silicon vias," or nano-TSVs . These are vertical interconnects that can connect up through the back side of the silicon to the bottom of the buried rails, like hundreds of tiny mineshafts. Once the nano-TSVs have been created below the transistors and BPRs, you can then deposit additional layers of metal on the back side of the chip to form a complete power-delivery network. Expanding on our earlier simulations, we at Arm found that just two layers of thick back-side metal was enough to do the job. As long as you could space the nano-TSVs closer than 2 micrometers from each other, you could design a back-side PDN that was four times as efficient as the front-side PDN with buried power rails and seven times as efficient as the traditional front-side PDN. The back-side PDN has the additional advantage of being physically separated from the signal network, so the two networks no longer compete for the same metal-layer resources. There's more room for each. It also means that the metal layer characteristics no longer need to be a compromise between what power routes prefer (thick and wide for low resistance) and what signal routes prefer (thin and narrow so they can make circuits from densely packed transistors). You can simultaneously tune the back-side metal layers for power routing and the front-side metal layers for signal routing and get the best of both worlds. Moving the power delivery network to the other side of the silicon—the “back side"—reduces voltage loss even more, because all the interconnects in the network can be made thicker to lower resistance. What's more, removing the power-delivery network from above the silicon leaves more room for signal routes, leading to even smaller logic circuits and letting chipmakers squeeze more transistors into the same area of silicon. Chris Philpot/IMEC In our designs at Arm, we found that for both the traditional front-side PDN and front-side PDN with buried power rails, we had to sacrifice design performance. But with back-side PDN the CPU was able to achieve high frequencies and have electrically efficient power delivery. You might, of course, be wondering how you get signals and power from the package to the chip in such a scheme. The nano-TSVs are the key here, too. They can be used to transfer all input and output signals from the front side to the back side of the chip. That way, both the power and the I/O signals can be attached to solder balls that are placed on the back side. Simulation studies are a great start, and they show the CPU-design-level potential of back-side PDNs with BPR. But there is a long road ahead to bring these technologies to high-volume manufacturing. There are still significant materials and manufacturing challenges that need to be solved. The best choice of metal materials for the BPRs and nano-TSVs is critical to manufacturability and electrical efficiency. Also, the high-aspect-ratio (deep but skinny) trenches needed for both BPRs and nano-TSVs are very difficult to make. Reliably etching tightly spaced, deep-but-narrow features in the silicon substrate and filling them with metal is relatively new to chip manufacture and is still something the industry is getting to grips with. Developing manufacturing tools and methods that are reliable and repeatable will be essential to unlocking widespread adoption of nano-TSVs. Furthermore, battery-powered SoCs, like those in your phone and in other power-constrained designs, already have much more sophisticated power-delivery networks than those we've discussed so far. Modern-day power delivery separates chips into multiple power domains that can operate at different voltages or even be turned off altogether to conserve power. (See " A Circuit to Boost Battery Life ," IEEE Spectrum, August 2021.) In tests of multiple designs using three varieties of power delivery, only back-side power with buried power rails [red] provides enough voltage without compromising performance. Chris Philpot Thus, back-side PDNs and BPRs are eventually going to have to do much more than just efficiently deliver electrons. They're going to have to precisely control where electrons go and how many of them get there. Chip designers will not want to take multiple steps backward when it comes to chip-level power design. So we will have to simultaneously optimize design and manufacturing to make sure that BPRs and back-side PDNs are better than—or at least compatible with—the power-saving IC techniques we use today. The future of computing depends upon these new manufacturing techniques. Power consumption is crucial whether you're worrying about the cooling bill for a data center or the number of times you have to charge your smartphone each day. And as we continue to shrink transistors and ICs, delivering power becomes a significant on-chip challenge. BPR and back-side PDNs may well answer that challenge if engineers can overcome the complexities that come with them. This article appears in the September 2021 print issue as "Power From Below." Keep Reading ↓Show less

American Electric Power Investments

15 Investments

American Electric Power has made 15 investments. Their latest investment was in Urbint as part of their Series C on August 8, 2021.

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American Electric Power Investments Activity

investments chart

Date

Round

Company

Amount

New?

Co-Investors

Sources

8/24/2021

Series C

Urbint

$60M

Yes

Blue Bear Capital, Energize Ventures, Energy Impact Partners, National Grid Partners, OGCI Climate Investments, and Salesforce Ventures

4

5/4/2021

Series D

Mainspring Energy

$95M

No

40 North Ventures, Bill Gates, Chevron Technology Ventures, ClearSky, Devonshire Investors, Equinor, Fidelity Investments, KCK, Khosla Ventures, and Princeville Global

2

8/5/2020

Series H - II

Chargepoint

$127M

No

Braemar Energy Ventures, Chevron Technology Ventures, ClearVision Equity Partners, CPP Investments, GIC, Linse Capital, and Quantum Energy Partners

17

11/28/2018

Series H

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$99M

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10

5/31/2018

Series A

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$99M

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10

Date

8/24/2021

5/4/2021

8/5/2020

11/28/2018

5/31/2018

Round

Series C

Series D

Series H - II

Series H

Series A

Company

Urbint

Mainspring Energy

Chargepoint

Subscribe to see more

Subscribe to see more

Amount

$60M

$95M

$127M

$99M

$99M

New?

Yes

No

No

Subscribe to see more

Subscribe to see more

Co-Investors

Blue Bear Capital, Energize Ventures, Energy Impact Partners, National Grid Partners, OGCI Climate Investments, and Salesforce Ventures

40 North Ventures, Bill Gates, Chevron Technology Ventures, ClearSky, Devonshire Investors, Equinor, Fidelity Investments, KCK, Khosla Ventures, and Princeville Global

Braemar Energy Ventures, Chevron Technology Ventures, ClearVision Equity Partners, CPP Investments, GIC, Linse Capital, and Quantum Energy Partners

Sources

4

2

17

10

10

American Electric Power Portfolio Exits

5 Portfolio Exits

American Electric Power has 5 portfolio exits. Their latest portfolio exit was Chargepoint on February 26, 2021.

Date

Exit

Companies

Valuation
Valuations are submitted by companies, mined from state filings or news, provided by VentureSource, or based on a comparables valuation model.

Acquirer

Sources

2/26/2021

Reverse Merger

$991

Switchback Energy Acquisition

4

00/00/0000

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10

00/00/0000

Subscribe to see more

Subscribe to see more

$991

Subscribe to see more

10

00/00/0000

Subscribe to see more

Subscribe to see more

$991

Subscribe to see more

10

00/00/0000

Subscribe to see more

Subscribe to see more

Subscribe to see more

10

Date

2/26/2021

00/00/0000

00/00/0000

00/00/0000

00/00/0000

Exit

Reverse Merger

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Companies

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Valuation

$991

$991

$991

Acquirer

Switchback Energy Acquisition

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Subscribe to see more

Subscribe to see more

Subscribe to see more

Sources

4

10

10

10

10

American Electric Power Acquisitions

3 Acquisitions

American Electric Power acquired 3 companies. Their latest acquisition was Sempra Renewables on February 12, 2019.

Date

Investment Stage

Companies

Valuation
Valuations are submitted by companies, mined from state filings or news, provided by VentureSource, or based on a comparables valuation model.

Total Funding

Note

Sources

2/12/2019

$991

Acquired

1

1/6/2012

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$99M

Subscribe to see more

10

11/23/1998

Acquired

Subscribe to see more

$991

$99M

Subscribe to see more

10

Date

2/12/2019

1/6/2012

11/23/1998

Investment Stage

Acquired

Companies

Subscribe to see more

Subscribe to see more

Valuation

$991

$991

Total Funding

$99M

$99M

Note

Acquired

Subscribe to see more

Subscribe to see more

Sources

1

10

10

American Electric Power Partners & Customers

10 Partners and customers

American Electric Power has 10 strategic partners and customers. American Electric Power recently partnered with Adapt2 Solutions on November 11, 2020.

Date

Type

Business Partner

Country

News Snippet

Sources

11/16/2020

Vendor

Adapt2 Solutions

United States

Adapt2 Solutions, Inc. Energy Market Solutions AEP Transforms Back Office ISO Operations, Selects Adapt2 Solutions to Streamline and Enhance ISO Settlements and Allocations.

HOUSTON , Texas -LRB- November 16 , 2020 -RRB- -- Adapt2 Solutions , a leading provider of AI enabled multi-market operations and trading software , today announced a new partnership with American Electric Power to digitally transform back office operations in the PJM and SPP energy markets .

1

3/18/2020

Vendor

Westinghouse

United States

WESTINGHOUSE WINS FUEL CONTRACT EXTENSION FOR AMERICAN ELECTRIC POWER’S D.C. COOK NUCLEAR PLANT.

`` This contract extension illustrates the strong , long-time partnership we have with American Electric Power , '' said Patrick Fragman , Westinghouse president and chief executive officer .

1

3/18/2020

Vendor

Westinghouse Electric

United States

Westinghouse Wins Fuel Contract Extension for American Electric Power’s D.C. Cook Nuclear Plant.

`` This contract extension illustrates the strong , long-time partnership we have with American Electric Power , '' said Patrick Fragman , Westinghouse Electric Company president and chief executive officer .

1

11/5/2019

Vendor

Subscribe to see more

Subscribe to see more

Subscribe to see more

10

4/24/2019

Vendor

Subscribe to see more

Subscribe to see more

Subscribe to see more

10

Date

11/16/2020

3/18/2020

3/18/2020

11/5/2019

4/24/2019

Type

Vendor

Vendor

Vendor

Vendor

Vendor

Business Partner

Adapt2 Solutions

Westinghouse

Westinghouse Electric

Country

United States

United States

United States

Subscribe to see more

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News Snippet

Adapt2 Solutions, Inc. Energy Market Solutions AEP Transforms Back Office ISO Operations, Selects Adapt2 Solutions to Streamline and Enhance ISO Settlements and Allocations.

HOUSTON , Texas -LRB- November 16 , 2020 -RRB- -- Adapt2 Solutions , a leading provider of AI enabled multi-market operations and trading software , today announced a new partnership with American Electric Power to digitally transform back office operations in the PJM and SPP energy markets .

WESTINGHOUSE WINS FUEL CONTRACT EXTENSION FOR AMERICAN ELECTRIC POWER’S D.C. COOK NUCLEAR PLANT.

`` This contract extension illustrates the strong , long-time partnership we have with American Electric Power , '' said Patrick Fragman , Westinghouse president and chief executive officer .

Westinghouse Wins Fuel Contract Extension for American Electric Power’s D.C. Cook Nuclear Plant.

`` This contract extension illustrates the strong , long-time partnership we have with American Electric Power , '' said Patrick Fragman , Westinghouse Electric Company president and chief executive officer .

Subscribe to see more

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Sources

1

1

1

10

10

American Electric Power Team

7 Team Members

American Electric Power has 7 team members, including current Chief Financial Officer, Brian Tierney.

Name

Work History

Title

Status

Brian Tierney

Chief Financial Officer

Current

Lisa M. Barton

Chief Operating Officer

Current

Jeff Fleeman

Managing Director

Current

Michael G Morris

Chief Executive Officer, President

Former

Mike Rencheck

Public Service Enterprise Group, and AREVA Group

President, Senior Vice President

Former

Name

Brian Tierney

Lisa M. Barton

Jeff Fleeman

Michael G Morris

Mike Rencheck

Work History

Public Service Enterprise Group, and AREVA Group

Title

Chief Financial Officer

Chief Operating Officer

Managing Director

Chief Executive Officer, President

President, Senior Vice President

Status

Current

Current

Current

Former

Former

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