(marketscreener.com) Third consecutive year of ISO 26262 “Fit for Purpose – Tool Confidence Level 1” of Magillem system-on-chip integration automation software productsCAMPBELL, Calif., Nov.  28, 2023   -- Arteris, Inc. , a leading provider of system IP which accelerates system-on-chip  creation, today announced that its Magillem SoC integration...https://www.marketscreener.com/quote/stock/ARTERIS-INC-128691363/news/Arteris-Celebrates-3-691-7496-Year-of-Automotive-ISO-26262-TCL1-Functional-Safety-Compliance-for-45451897/?utm_medium=RSS&utm_content=20231128

Arteris Celebrates 3&#691;&#7496; Year of Automotive ISO 26262 TCL1 Functional Safety Compliance for Magillem SoC Integration Automation

Campbell, California, UNITED STATES
CAMPBELL, Calif., Nov.  28, 2023  (GLOBE NEWSWIRE) -- Arteris, Inc. (Nasdaq: AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that its Magillem SoC integration automation software products have achieved their third consecutive year of Automotive ISO 26262:2018 Tool Confidence Level 1 (TCL1) certification by TÜV SÜD. This milestone expands upon Arteris’ ongoing commitment to delivering functional safety capabilities for mission-critical applications across the entire product portfolio. ISO 26262 is an internationally recognized standard for ensuring functional safety in the automotive industry. It establishes comprehensive guidelines for designing and testing electrical and electronic systems in vehicles, ultimately reducing risks and accidents associated with automotive technology. "Automotive semiconductor manufacturers, component suppliers and OEMs are under increasing pressure to deliver innovative technology with the highest levels of functional safety,” said Günter Greil, head of department at TÜV SÜD. “Arteris’ Magillem SoC integration automation software continues to meet the rigorous requirements of ISO 26262 TCL1, which in turn allows their customers to reduce the time spent on tool qualification and focus instead on product development.”
“We are pleased that Arteris’ Magillem SoC integration products recently passed their annual factory inspection, which reaffirms their sustained level of high-quality development demanded by ISO 26262 TCL1,” said Stefano Lorenzini, functional safety fellow at Arteris. “This achievement reflects our ongoing pursuit of excellence, ensuring our tools play a vital role in advancing automotive safety, which allows our customers to design the innovative technology of tomorrow while ensuring the utmost quality and reliability.”
This accomplishment further reinforces Arteris’ position as a leader in system IP and SoC integration automation, simplifying the chip certification process and ensuring the highest functional safety standards in the automotive industry. For more information about Arteris automotive solutions, please visit arteris.com/solutions/automotive/ . To learn more about Arteris ISO 26262-certified products, please visit arteris.com/solutions/safety/ . About Arteris
Arteris is a leading provider of system IP for accelerating system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next. Learn more at arteris.com . © 2004-2023 Arteris, Inc. All rights reserved worldwide. Arteris, Arteris IP, the Arteris IP logo, and the other Arteris marks found at https://www.arteris.com/trademarks are trademarks or registered trademarks of Arteris, Inc. or its subsidiaries. All other trademarks are the property of their respective owners.

Arteris Celebrates 3ʳᵈ Year of Automotive ISO 26262 TCL1 Functional Safety Compliance for Magillem SoC Integration Automation

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Accellera sponsored a luncheon panel discussion at #60DAC, so I registered and attended to learn more about one of the newest working groups for Clock Domain Crossing (CDC). An overview of Accellera was provided by Lu Dai, then the panel discussion was moderated by Paul McLellan of Cadence , with the following panel members:
Accellera Panel, Clock Domain Crossing
Panel Opening Remarks
Anupam Bakshi – has been with Agnisys since 2007, and before that with Gateway Design Automation – where Verilog was invented. Agnisys has been offering CDC automation tools, and is a member of the Accellera working group on CDC standards. He recommended to avoid meta-stability by using a spec-driven and synchronization approach, along with correct by construction design automation. This approach uses declarative attributes, and then engineers simply run the tool. Frank Schirrmeister – he’s the VP of business development at Arteris, and before that at Cadence. Arteris has a Network On Chip (NOC) focus, and they acquired companies like Semifore to gain system IP, and Magillem to add ISO 26262 and IP-XACT expertise. Frank recommends the generation of registers from a higher-level specification along with CDC logic. As IP for an SoC is provided by multiple vendors, it makes sense to have a CDC standard to ensure that all IP that is integrated will work reliably, so there’s a need for a common intent language. Dammy Olopade – he’s the working group chair for CDC and a principal engineer at Intel. The new working group was proposed in September 2022, then approved in December, and there are now 96 participants from 22 companies so far. The draft LRM for the CDC is due around December 2023. Ping Yeung – at Nvidia he is a Senior Manager of Formal Verification. Today bringing up IP blocks with proper CDC checks is very tedious, and too time consuming, so a CDC standard with hierarchy is welcomed. It will allow engineers to focus on CDC at the top level only. They really want to mix internal and external IP blocks easily. Assertions will ensure that models are used correctly, to verify interface properties, constraints and assumptions. Q&A
Q: Paul – why a CDC standard now? A: Dammy – at one time all lines of code came from one design team, not now, it’s multiple vendors now. The new model has IP blocks from many different vendors. With so many IP vendors and IP users,  a CDC standard is required. A: Frank – Systemic complexity has grown too large, so a CDC standard is required to keep issues in control. The implementation details now impact the architecture choices. A common language and vocabulary become more important now. A: Anupam – customers request more CDC validation in their IP integration challenges so we have to act now. A: Ping – also internal IP blocks must be checked to see if they are being reused properly. What can we do if the original designer is gone? A: Frank – Since 2000 we’ve been doing abstraction at the same levels, but now we can abstract register generation automatically from a high-level. We now have virtual platforms for HW and SW design. Q: Paul – what about asynchronous input signals to a chip? A: Dammy – there has to be a specification for design intentions. What is the spec? How do we design to meet the spec? The first spec should come along in the September time frame. We need to make sure that our clock never glitches, to keep it a synchronous design. A: Frank – we know how to handle that challenge. We see different clock domains, and then insert the required logic, however the validation bit is a focus of new WG. If your PLLs start to jitter, then video and audio can drift out of synch. A: Ping – we know how to handle asynchronous signals with known solutions. EDA tools can find CDC domain crossings. When the interfaces have been verified per IP block, how do we capture that verification at the top level, instead of re-verifying all over again? Q: Paul – how many clock domains are being used today? A: Anupam – 3-10 is a typical range. A: Frank – hundreds have been seen. Even the number of re-used IP blocks can be in the hundreds now. Formal verification can be used at full-chip level, but different tools return different results, so some violations are false-positive. IP integrators and IP vendors need to have the same understanding on clock domains. Q: Paul – what’s next for IP integration after CDC? A: Ping – Reset domain crossing needs to be standardized. A: Anupam – what about correct by design approaches? The specification has not been rigorous enough. A: Frank – integration issues with IP is still a tough issue. What about CDC and safety issues interacting together? Can we ever go beyond RTL abstractions? A: Anupam – what about FSM and datapath standards? Standards are only at the interfaces for now. A: Frank – what about MBSE using SysML? Can we get to that level? A: Dammy – if we already have a working system, then let’s keep working EDA tools then add innovative new tools. Power and performance challenges cannot be easily solved with today’s tools. Q: Dennis Brophy – what about manufacturing issues and using chiplets? A: Frank – I asked at UCIe about PHYs working together. Are there any plugfest possibilities? It’s a new layer of complexity. A: Dammy – there is no interoperable language for CDC now. So we should follow a more correct by construction approach to enable chiplets. Summary
This panel discussion was fast-paced and the engineers in the audience were actively asking questions and approaching the panelists after the discussion to get their private questions answered. CDC standardization is moving along, and interested engineers are encouraged to join in the working group discussion sessions. If your company is not already an Accellera member, please visit https://accellera.org/about/join for more information on how to join and participate. Related Blogs

Accellera and Clock Domain Crossing at #60DAC – Semiwiki

This coming week from July 9th to July 13th, experts from all over the world will descend on the Moscone Center in San Francisco to discuss aspects of what we call “Electronic Design Automation” (EDA) and typically associate with hardware development. There will be many celebratory elements this year, given the milestone of 60 years. Industry luminary Alberto Sangiovanni Vincentelli will give one of the keynotes called “ Corsi e Ricorsi: Here We Go Again .” Some presentations will likely worry about staffing – Joe Sawicki ‘s talk is titled “ Systems 2030 – What’s Needed to Succeed in the Next Decade of Design without Resorting to Human Cloning ,” only to be followed later in the week by a glimmer of hope for the future of EDA with a talk by the youngest presenter, ever, at DAC. Ham Radio Operator (KJ7NLL) Zeke Wheeler will use his summer break at school to talk about his efforts to speak to space with self-built equipment in his talk “ DIY Orbital Tracking System for Space Communication: A Project to Contact the International Space Station .”
DAC’s 60th anniversary highlights. What happened to system design and system on chip (SoC) integration? For me, this will be the 25th DAC that I am attending. During my first DAC in 1998, Gary Smith had just coined the term “Electronic System Level” (ESL), and High-Level Synthesis was the year’s hot topic. The industry has made great strides since then, albeit not always in the predicted direction. High-level synthesis has “simply” become the front end for digital implementation flows. It has never grown up to synthesize many whole chips, but it is these days critical to block development, porting between semiconductor technologies, and Engineering Change Order (ECO) management. Another topic – the increased criticality of hardware/software co-design and the complexity of chip integration – was on the horizon back then already and will be a key theme at this year’s DAC, too, um, still. Modern System-on-Chip (SoC) devices involve hundreds of functional intellectual property (IP) blocks, including externally acquired and internally developed ones. These blocks require careful integration to ensure the SoC operates effectively. And the trend towards chipset-based design – probably the hottest topic this DAC – only amplifies this trend as design teams consider integration across chip boundaries. SoC integration involves managing extensive metadata that describes each IP and has been mostly a manual process in the past, leading to data alignment challenges and a lack of a single source of truth. Manual approaches often resulted in missed deadlines and failed revenue targets. The “ Virtual Socket Interface Alliance ” was a hot topic in 1998. Since then, a solution came with IP-XACT, a metadata format developed to manage and integrate SoC IPs. While IP-XACT specifies metadata representation, design teams need the appropriate tools and environment to utilize it fully. Companies that had to automate complex, error-prone tasks, ensure repeatability, and streamline the IP integration process have often created proprietary infrastructures that can become complex and difficult to maintain, especially for startups. Arteris will show at this DAC its SoC integration offerings allowing design teams to build their automation infrastructure and facilitate SoC integration based on a single source of truth. They can seamlessly integrate IPs regardless of their IP-XACT model status, ensuring their semantic and syntactic correctness. The Magillem toolset helps users create the design hierarchy for integrating all IPs. It’s about connecting different IPs and configuring and instantiating each IP, creating interfaces, and building each IP into the design hierarchy. The Magillem toolset adapts to the underlying interconnect fabrics used by the SoC designers – like FlexNoC and Ncore – and provides ways to rearrange the design hierarchy easily. This capability assists design teams in upgrading individual IPs and organizing their physical layout and can be fully automated and used in a continuous integration pipeline. Hardware/software co-design is a critical part of SoC integration and plays a role here too. Magillem Registers translates the specification of registers into executable design code by automatically importing the register descriptions from different sources and formats into IP-XACT. It automatically checks the accuracy of the information – like overlaps, configurability, reserved empty spaces, and more – and enables close collaboration between hardware, software, and tech doc teams through a single source of truth methodology for consistently generated data. Applying this process results in better quality design and increased productivity. An example of a design flow with a single source of truth. (Source: Arteris)
The IP Engineering Track at DAC
For my 25th DAC, I was invited as a member of the Executive Committee to chair the IP portion of the Engineering Track. Like the DAC research track overall, the Engineering track saw a significant increase in submissions for its 60th birthday. With the help of my extraordinary Technical Program Committee (TPC) Himanshu Sanghavi , Navid Farazmand , Vidyasagar Ganesan , Randy Fish , and Shankar Hemmady , led by Henning Spruth as TPC chair, we came up with a program I am very proud of. For this year’s IP Engineering Track, we selected 24 presentations in four sessions:
What’s next
We live in genuinely unique times for semiconductor design. Artificial intelligence and machine learning (AI/ML) for EDA development and EDA development to enable AI/ML semiconductor components seem to create a circular loop that only gets faster. Traditional printed circuit board (PCB) design and semiconductor development move closer to each other as PCBs get smaller and become chiplet-based designs while in parallel, SoCs meet the reticle cost/yield limits and disaggregate, you guessed it, into chiplet-based designs, too. Beyond the classic EDA topics, we have application-specific designs for automotive, enterprise computing, data center, industrial, and consumer applications, horizontal solutions for security, safety, and hardware/software, and of course, the move toward system design, including mechanical, EM and many more aspects to consider. And then, there are the impacts of generative AI, workforce development, and many other items to discuss. DAC is the place to be next week. I look forward to celebrating DAC’s 60th birthday with you and discussing how EDA will shape the next decade.

The Design Automation Conference Turns 60! What’s Hot? What’s Next?

(19.7)% - (9.7)%
The guidance provided above are forward-looking statements and reflect our expectations as of today's date. Actual results may differ materially. Refer to the section titled "Forward-Looking Statements" below for information on the factors, among others, that could cause our actual results to differ materially from these forward-looking statements. Non-GAAP gross profit, Non-GAAP gross margin, Non-GAAP operating loss, Non-GAAP operating loss margin, Non-GAAP net loss, Non-GAAP net loss per share, free cash flow and free cash flow margin are Non-GAAP financial measures. Additional information on Arteris’ historic reported results, including a reconciliation of these Non-GAAP financial measures to their most comparable GAAP measures, is included in the financial tables below. A reconciliation of Non-GAAP guidance measures reported above to corresponding GAAP measures is not available on a forward-looking basis without unreasonable effort due to the uncertainty of expenses that may be incurred in the future, although it is important to note that these factors could be material to Arteris' results computed in accordance with GAAP. Definitions of the other business metrics used in this press release including ACV, active customers, confirmed design starts and RPO are included below under the heading “Other Business Metrics.”
Conference Call
Arteris will host a conference call today on February 28, 2023 to review its fourth quarter and full year 2022 financial results and to discuss its financial outlook. A live webcast will also be available in the Investor Relations section of Arteris’ website at: https://ir.arteris.com/events-and-presentations
A replay of the webcast will be available in the Investor Relations section of the company’s web site approximately two hours after the conclusion of the call and remain available for approximately 30 calendar days. About Arteris
Arteris IP (Nasdaq: AIP) provides system-on-chip (SoC) system IP consisting of network-on-chip (NoC) interconnect IP and IP deployment technology to accelerate system-on-chip (SoC) semiconductor development and integration for a wide range of applications from AI to automobiles, mobile phones, IoT, cameras, SSD controllers, and servers for customers such as Bosch, Mobileye, Samsung, Toshiba and NXP. Arteris IP products include the Ncore® cache coherent and FlexNoC® non-coherent interconnect IP, the CodaCache® standalone last level cache, and optional Resilience Package (ISO 26262 functional safety), FlexNoC AI Package, and PIANO® automated timing closure capabilities. Our IP deployment products provide intelligent automation that accelerates the development and increases the quality of SoC hardware designs and their associated software and firmware, verification and simulation platforms, and specifications and customer documentation. Customer results obtained by using Arteris IP products include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. Investor Contacts:
+1 617 542 6180
Forward-Looking Statements
This press release contains forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995, as amended, including but not limited to, statements regarding our future financial and operating performance, including our GAAP and Non-GAAP guidance for the fourth quarter and full year 2022; our market opportunity and its potential growth; our position within the market and our ability to drive customer value; and our ability to make progress even in a challenging economic environment. The words "may," "might," "will," "could," "would," "should," "expect," "plan," "anticipate," "intend," "believe," "expect," "estimate," "seek," "predict," "future," "project," "potential," "continue," "target" and similar words or expressions are intended to identify forward-looking statements, although not all forward-looking statements contain these identifying words. Any forward-looking statements contained herein are based on our historical performance and our current plans, estimates and expectations and are not a representation that such plans, estimates, or expectations will be achieved. These forward-looking statements represent our expectations as of the date of this press release. Subsequent events may cause these expectations to change, and we disclaim any obligation to update the forward-looking statements in the future, except as required by law. These forward-looking statements are subject to known and unknown risks and uncertainties that may cause actual results to differ materially from our current expectations. Important factors that could cause actual results to differ materially from those anticipated in our forward-looking statements include, but are not limited to, the significant competition we face from larger companies and third-party providers; our history of net losses; whether semiconductor companies in the automotive market, enterprise computing market, communications market, consumer electronics market, and industrial markets incorporate our solutions into their end products and the growth and economic stability of these end markets; our ability to attract new customers and the extent to which our customers renew their subscriptions for our solutions; the ability of our customers’ end products achieving market acceptance or growth; our ability to sustain or grow our licensing revenue; our ability, and the cost, to successfully execute on research and development efforts; the occurrence of product errors or defects in our solutions; if we fail to offer high-quality support; the occurrence of macro-economic conditions that adversely impact us, our customers and their end product markets; the effects of geopolitical conflicts, such as the military conflict between Russia and Ukraine; the range of regulatory, operational, financial and political risks we are exposed to as a result of our dependence on international customers and operations; our ability to protect our proprietary technology and inventions through patents and other IP rights; whether we are subject to any liabilities or fines as a result of government regulation, including import, export and economic sanctions laws and regulations; the occurrence of a disruption in our networks or a security breach; risks associated with doing business in China; and the other factors described under the heading “Risk Factors” in our Annual Report on Form 10-K for the quarter ended December 31, 2022 to be filed with the Securities and Exchange Commission (SEC) on February 28, 2023. All forward-looking statements reflect our beliefs and assumptions only as of the date of this press release. We undertake no obligation to update forward-looking statements to reflect future events or circumstances. Our results for the quarter ended December 31, 2022 are not necessarily indicative of our operating results for any future periods. Arteris, Inc
(in thousands, except share and per share data)
(Unaudited)
Non-GAAP Financial Measures
To supplement our financial results, which are prepared and presented in accordance with GAAP, we use certain Non-GAAP financial measures, as described below, to understand and evaluate our core performance. These Non-GAAP measures, which may be different than similarly-titled measures used by other companies, are presented to enhance investors’ overall understanding of our financial performance and should not be considered a substitute for, or superior to, the financial information prepared and presented in accordance with GAAP. We define "Non-GAAP Gross Profit and Non-GAAP Gross Margin" as GAAP gross profit and GAAP gross margin, adjusted for stock-based compensation expense included in cost of revenue. We define “Non-GAAP Loss from Operations” as our income (loss) from operations adjusted to exclude stock-based compensation, acquisition costs and amortization of acquired intangible assets. We define “Non-GAAP Net Loss” as our net income (loss) adjusted to exclude stock-based compensation, acquisition costs, amortization of acquired intangible assets and gain on extinguishment of debt. We define “Non-GAAP EPS”, as our Non-GAAP Net Income (Loss) divided by our GAAP weighted-average number of shares outstanding for the period on a diluted basis. Management uses Non-GAAP EPS to evaluate the performance of our business on a comparable basis from period to period. The above items are excluded from our Non-GAAP Gross Profit, Non-GAAP Income (Loss) from Operations and Non-GAAP Net Income (Loss) because these items are non-cash in nature, or are not indicative of our core operating performance, and render comparisons with prior periods and competitors less meaningful. We believe Non-GAAP Gross Profit, Non-GAAP Income (Loss) from Operations and Non-GAAP Net Income (Loss) provide useful supplemental information to investors and others in understanding and evaluating our results of operations, as well as provide a useful measure for period-to-period comparisons of our business performance. We define free cash flow as net cash (used in) provided by operating activities less cash used for purchases of property and equipment. We believe that free cash flow is a useful indicator of liquidity that provides information to management and investors, even if negative, about the amount of cash used in our operations other than that used for investments in property and equipment. Other Business Metrics
Annual Contract Value (ACV) – we define Annual Contract Value for an individual customer agreement as the total fixed fees under the agreement divided by the number of years in the agreement term. Our total ACV is the aggregate ACVs for all our customers as measured at a given point in time. Total fixed fees includes licensing, support and maintenance and other fixed fees under IP licensing or software licensing agreements but excludes variable revenue derived from licensing agreements with customers, particularly royalties. We monitor ACV to measure our success and believe the increase in the number shows our progress in expanding our customers’ adoption of our solutions. ACV fluctuates due to a number of factors, including the timing, duration and dollar amount of customer contracts. Active Customers – we define Active Customers as customers who have entered into a license agreement with us that remains in effect. The retention and expansion of our relationships with existing customers are key indicators of our revenue potential. Confirmed Design Starts – we define Confirmed Design Starts as when customers confirm their commencement of new semiconductor designs using our interconnect IP and notify us. Confirmed Design Starts is a metric management uses to assess the activity level of our customers in terms of the number of new semiconductor designs that are started using our interconnect IP in a given period. We believe that the number of Confirmed Design Starts is an important indicator of the growth of our business and future royalty revenue trends. Remaining Performance Obligations (RPO) – we define Remaining Performance Obligations as the amount of contracted future revenue that has not yet been recognized, including both deferred revenue and contracted amounts that will be invoiced and recognized as revenue in future periods. Arteris, Inc.
(In thousands, except share and per share data)
(unaudited)
(1) Represents the amortization expenses of our intangible assets attributable to the Magillem acquisition. (2) Includes advisory, legal, accounting, valuation, and other professional or consulting fees associated with the Magillem and Semifore acquisitions and recorded in general and administrative. (3) Presented within interest and other expense, net on the consolidated statements of loss. (4) Our GAAP tax provision is primarily related to foreign withholding taxes and income tax in profitable foreign jurisdictions. We maintain a full valuation allowance against our deferred tax assets in the US. Accordingly, there is no significant tax impact associated with these Non-GAAP adjustments. (5) Reflects the aggregate adjustments made to reconcile Non-GAAP Net Loss to our net loss as noted in the above table, divided by the GAAP diluted weighted average number of shares of the relevant period. Free Cash Flow

Arteris Announces Financial Results for the Fourth Quarter and Full Year 2022 and Estimated First Quarter and Full Year 2023 Guidance

Arteris is a company that specializes in system IP, focusing on the acceleration of system-on-chip (SoC) development within the electronics industry. The company offers products such as network-on-chip (NoC) interconnect IP and system integration automation tools, which are designed to optimize SoC performance, reduce power consumption, and accelerate time to market. Arteris primarily serves sectors such as the automotive, communications, consumer electronics, enterprise computing, and industrial sectors. It was founded in 2003 and is based in Campbell, California.

Arteris

The first technical fruit of the partnership is the validation of full compliance of Arteris IP interconnects with the Magillem environment .

Arteris IP and Magillem Partner to Create Integrated System-on-Chip Architecture Environment.

Imperas is focused on delivering technology in the Electronic Design Automation (EDA) space. By blending hardware and software technologies and design processes together, Imperas provides methodologies, technologies and products to enable the efficient programming, debug, and verification of Multiprocessor Systems-on-Chip (MPSoCs). With an engineering base in the UK, Imperas distributes its products to customers worldwide.

Imperas

Renesas Electronics (TSE: 6723) manufactures semiconductor products. It manufactures audio switches, analog switches, ambient light sensors, automotive radar sensors, and more. It serves industries such as automotive, consumer electronics, healthcare, and more. The company was founded in 2002 and is based in Tokyo, Japan.

Renesas Electronics

NetSpeed Systems provides on-chip network IPs to SoC designers for a wide range of markets from mobile to high-performance computing and networking. NetSpeed's on-chip network platform delivers significant time-to-market advantages through a system-level approach, a high level of user-driven automation and state-of-the-art algorithms.

NetSpeed Systems

Methodics is a provider of design data management (DM) tools that improve the efficiency and collaboration of integrated circuit (IC) design. Its ProjectIC system is an integrated platform for managing SoC realization, reducing the time, complexity, and costs involved in IP-based design approaches. Its VersIC DM tools integrate industry-standard software configuration management (SCM) tools, such as the Perforce and Subversion version control systems into the hardware design environment to provide a more efficient global collaboration experience.

On July 20, 2020, Methodics was acquired by Perforce Software, terms of the transaction were not disclosed.

Methodics

Acquired

Magillem is a provider of complex design flow and content management software solutions. The company provides EDA front-end design environment software that provides integration across specification, design, and documentation processes.

On October 1st, 2020, Magillem was acquired by Arteris. Terms of the transaction were not disclosed.

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